1. Field of the Invention
The present invention relates to an arbiter and process for implementing the same which permits flexible prioritization of access to a bus.
2. Art Background
In a computer system, buses are typically used to interconnect data and address paths among multiple components of the system. This limits the number of physical connections required among the different components by multiplexing access by the different components to the bus lines. However, quite frequently multiple components request access to the bus on or about the same time. It is preferable that access is granted based on a form of priority of access to the bus. Typically, an arbiter is employed to arbitrate access to the bus. Many different arbitration schemes exist and are well known; however, these schemes are typically fixed in priority and do not permit the arbiter to be dynamically modified to change the priority of arbitration. Although some arbiters permit devices to modify priority, this often requires a reassignment of the device's input to the arbiter. The reassignment process is not dynamic and requires that the device request line to the arbiter be physically moved to a different arbiter input representative of a different level of priority.